There are two distinct classes of signals in SV: wires and signals. These differ in two respects. First, a wire has no memory. It does not maintain its previous state in the case it is not assigned. Rather, the value of an unassigned wire is undefined. A register on the other hand will maintain its previous state when unassigned. Second, a value assigned to a wire propagates in exactly zero time. On the other hand, a register entails exactly one unit of delay: a value assigned to a register becomes visible exactly one time unit later.
For example, suppose we have:
wire x;
reg y;
always
begin
x = y;
end
always
begin
y = z;
end
The net result of this code is that the value of x lags the
value of z by exactly one time unit. Note that although the result
of an assignment to a register becomes visible one time unit later, the
assignment statement itself executes in zero time. For example, consider
the following block of code:
wire x,z;
reg y;
always
begin
y = z;
x = y;
end
The effect of this code is that at all times x = z, whereas the
register y lags x and z by one time unit. That is,
within the always block, all statements except wait statements
appear to execute in zero time. Thus, the assignment y = z
executes in zero time, setting the value of y and then this
value is assigned to x, again in zero time. However, an observer
outside the always block sees the value of y with one
time unit of delay. Another example:
reg [31:0] y;
initial y = 0;
always
begin
y = y + 1;
y = y + 1;
end
In this case, the observed sequence of values of y is
0,2,4,6,.... That is, the always block executes both assignment
statements in exactly zero time, in effect adding 2 to y. This
effect is seen outside the block one time unit later.