An assignment is of the form
<signal> := <expr>;where <expr> is an expression that combines other signals using operators like ~ and &. Unlike an assignent in a typical ``procedural'' language, this assignment means exactly what it says: that <signal> is equal to <expr>. So for example, suppose we make the assignment
zip := foo & bar;
If foo and bar are as above, then
zip = 0;0;0;1;...
Note that this assignment says what to compute, but does not say when to compute it. Thus, for example, we might first compute the entire sequences foo and bar (or more accurately, finite subsequences), and then compute the sequence zip. Or, we might compute the first elements of all three sequences, then the second elements, and so on. This is a significant departure from hardware description languages such as verilog HDL, which explicitly schedule computations by means of an event queue. In SMV, the issues of what to compute and when to compute it are separated. Thus, the same program might be compiled into a highly parallel hardware implementation, or a completely sequential software implementation.